Split capacitor SAR ADC architectures have significant advantages from an analog implementation point of view. However, conventional split capacitor SAR ADCs are difficult to calibrate since the weight of the Least Significant Bit (LSB) of the split capacitor SAR ADC is not a function of the comparator decisions. As a consequence, it is difficult to estimate the LSB. However, the LSB weight is an important quantity. For example, if a split capacitor SAR ADC is used in a pipeline ADC, it is important to have an estimate for the LSB weight.
Hence, there may be a desired for an improved SAR ADC architecture.